Strategies for Optimising DRAM Repair

Abstract

Dynamic Random Access Memories (DRAM) are large complex devices, prone to
defects during manufacture. Yield is improved by the provision of redundant
structures used to repair these defects. This redundancy is often
implemented by the provision of excess memory capacity and programmable
address logic allowing the replacement of faulty cells within the memory
array.

As the memory capacity of DRAM devices has increased, so has the complexity
of their redundant structures, introducing increasingly complex restrictions
and interdependencies upon the use of this redundant capacity.

Currently redundancy analysis algorithms solving the problem of optimally
allocating this redundant capacity must be manually customised for each new
device. Compromises made to reduce the complexity, and human error, reduce
the efficacy of these algorithms.

This thesis develops a methodology for automating the customisation of these
redundancy analysis algorithms. Included are: a modelling language
describing the redundant structures (including the restrictions and
interdependencies placed upon their use), algorithms manipulating this model
to generate redundancy analysis algorithms, and methods for translating
those algorithms into executable code.

Finally these concepts are used to develop a prototype software tool capable
of generating redundancy analysis algorithms customised for a specified
device.