Mahoney, Patrick Francis (1995) Modelling and analysis of crosstalk in scaled CMOS interconnects. Masters thesis, Durham University.
The development of a general coupled RLC interconnect model for simulating scaled bus structures m VLSI is presented. Several different methods for extracting submicron resistance, inductance and capacitance parameters are documented. Realistic scaling dimensions for deep submicron design rules are derived and used within the model. Deep submicron HSPICE device models are derived through the use of constant-voltage scaling theory on existing 0.75µm and 1.0µm models to create accurate interconnect bus drivers. This complete model is then used to analyse crosstalk noise and delay effects on multiple scaling levels to determine the dependence of crosstalk on scaling level. Using this data, layout techniques and processing methods are suggested to reduce crosstalk in systems
|Item Type:||Thesis (Masters)|
|Award:||Master of Science|
|Copyright:||Copyright of this thesis is held by the author|
|Deposited On:||24 Oct 2012 15:10|