Characterisation of crosstalk defects in submicron CMOS VLSI interconnects

Abstract

The main problem addressed in this research work is a crosstalk defect, which is defined as an unexpected signal change due to the coupling between signals or power lines. Here its characteristic under 3 proposed models is investigated to find whether such a noise could lead to real logic faults in IC systems. As a result, mathematical analysis for various bus systems was established, with 3 main factors found to determine the amount of crosstalk: i) how the input buffers are sized; ii) the physical arrangements of the tracks; and iii) the number of switching tracks involved. Minimum sizes of the width and separation lead to the highest crosstalk while increasing in the length does not contribute much variation. Higher level of crosstalk is also found in higher metal layers due mainly to the reduced capacitance to the substrate. The crosstalk is at its maximum when the track concerned is the middle track of a bus connected to a weak buffer while the other signal lines are switching. From this information, the worse-case analysis for various bus configurations is proposed for 0.7, 0.5 and 0.35 µ CMOS technologies. For most of conventional logic circuits, a crosstalk as large as about a half of the supply voltage is required if a fault is to occur. For the buffer circuits the level of crosstalk required depends very much on the transition voltage, which is in turn controlled by the sizing of its n and p MOS transistors forming the buffer. It is concluded that in general case if crosstalk can be kept to be no larger that 30% of the supply voltage the circuit can be said to be very reliable and virtually free from crosstalk fault. Finally test structures are suggested so that real measurements can be made to verify the simulation results