We use cookies to ensure that we give you the best experience on our website. By continuing to browse this repository, you give consent for essential cookies to be used. You can read more about our Privacy and Cookie Policy.

Durham e-Theses
You are in:

Graphene Hall Sensors for Harsh Environment
Current Sensing

PETERS, AMY (2021) Graphene Hall Sensors for Harsh Environment
Current Sensing.
Doctoral thesis, Durham University.

Full text not available from this repository.
Author-imposed embargo until 20 October 2022.


Development of electronic devices which are capable of operating in harsh environments is a key enabler in the aerospace industry's move towards the More Electric Aircraft (MEA). The superlative material and electronic properties of graphene have generated significant interest in the development of next generation electronic devices. The use of graphene for development of highly sensitive graphene Hall effect sensors for use in power electronics modules is investigated, however it is found that conventional lithographic processing contaminates the surface of the graphene film often resulting in degradation of these properties.

A novel approach to fabricating high yield, reproducible graphene devices through the use of a Cu sacrificial layer is described. The use of such a sacrificial layer is studied and compared to conventional lithographic processing (no sacrificial layer), fabrication with an Al sacrificial layer (a method commonly used by graphene manufacturers) and commercial graphene sensors fabricated by the manufacturer of the CVD graphene films used in this study. Surface analysis in the form of Atomic Force Microscopy (AFM) and Raman spectroscopy is utilised, showing that graphene devices fabricated using a Cu sacrificial layer significantly reduces defect density over that of devices fabricated using both no sacrificial layer and Al sacrificial layer suggesting a reduction in surface doping of 60~\% over devices fabricated with no sacrificial layer. Height profiles of AFM images taken across devices additionally exhibit reduced surface roughness (8.8$\pm$0.20~nm) in comparison to the average RMS surface roughness of 16$\pm$0.60~nm and 17$\pm$0.40~nm observed across devices fabricated using no sacrificial layer and Al sacrificial layer respectively. Electrical characteristics additionally show that the use of a Cu sacrificial layer not only offers improved device sensitivity, carrier mobility and reduced carrier density but device yield is increased from 12~\% to 82~\% with variability in characteristics reduced from 40~\% to 10~\%. The graphene sensors developed using a Cu sacrificial layer are further optimised through external biasing in order to shift the Fermi level of the graphene towards the charge neutrality point, resulting in an increase in current related sensitivity of 165$\pm$16.5~V/AT observed in un-gated devices to 972$\pm$19.0~V/AT at the Dirac point.

Both high temperature and AC characteristics of devices are presented in order to examine the suitability of the graphene sensors for the desired application. Device characteristics taken up to 473~K are shown to exhibit a gaussian trend with temperature, largely attributed to evaporation of moisture absorbed to the surface either during processing or device storage. External gate biasing to reduce this effect is demonstrated with a reduction in the thermal coefficient of sensitivity from 4.5$\pm$0.18$\times$10$^3$~ppm/K to 0.50$\pm$0.025$\times$10$^3$~ppm/K observed when $V_G$$>$$V_{DIRAC}$. Devices still however exhibit a small gaussian trend with temperature. Vacuum annealing of devices show that this gaussian trend can be removed with characteristics post anneal exhibiting a linear trend with temperature and a significantly reduced thermal coefficient of just 0.27$\pm$0.014$\times$10$^3$~ppm/K. It is summarised that in order to successfully implement devices with a linear temperature dependance and reduced thermal coefficient, appropriate packaging needs to be developed in order to protect the surface of the graphene film post anneal. AC characteristics up to 250~kHz are analysed with devices having an observed cut off frequency of 200~kHz. This cut off is thought to be an inherent limitation of the test setup however this bandwidth is still a significant increase on the 120~kHz limit observed in commercial semiconducting Hall sensors.

Finally, the analysis of SiC JFETs is presented and utilised to develop a representative LTSpice model. The JFET SPICE modelling is shown with the simulated output characteristics shown to be within 9.0~\% of those extracted from functional devices, comparable to the variability seen in characteristics of manufactured devices ($\sim$~10~\%). LTSpice modelling is used to develop both the input and output circuitry that forms the final Hall sensor system made up of the input current bias, the PWM signal of which the Hall sensor will detect, buffering and differential amplification of the output signal and finally level shifting and filtering.

Item Type:Thesis (Doctoral)
Award:Doctor of Philosophy
Faculty and Department:Faculty of Science > Engineering, Department of
Thesis Date:2021
Copyright:Copyright of this thesis is held by the author
Deposited On:21 Oct 2021 10:38

Social bookmarking: del.icio.usConnoteaBibSonomyCiteULikeFacebookTwitter